Universal Emulations with Sublogarithmic Slowdown

The existence of bounded degree networks which can emulate the computation of any bounded degree network of the same size with logarithmic slowdown is well-known. The butterfly is an example of such a universal network. Leiserson was the first to introduce the concept of an area-universal network: a network with VLSI layout area A which can emulate any network of the same size and layout area with logarithmic slowdown. His results imply the existence of an N-node network with layout area O( N log2 N ) which can emulate any N-node planar network with O(1og N ) slowdown. The main results of this paper are: 0 There exists an N-node network with layout area O ( N log2 N ) which can emulate any Nnode planar network with O(log1og N ) slowdown. 0 The N-node butterfly (and hypercube) can emulate any network with VLSI layout area N2-' ( E > 0) with O(log1og N ) slowdown. We also discuss sublogarithmic bounds for the slowdown of emulations of arbitrary bounded degree networks. *This research supported in part by the NEC Research Institute. tThis research supported in part by the NEC Research Institute and by the Natural Sciences and Engineering Research Council of Canada under research grant OGP0137991.